By Virginia Williamson
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Extra info for Byte - March 1976
On ce locked, the oscillator will trac k the input signal over a ±70 percent range. Th e sum freq uency component of the ph ase detector output does modul ate the oscillator slightl y but was not considered to be a probl em. Thi s modulation ca n be dimini shed by increasing the loop filtering; howeve r, this redu ces the capture range which is undesirabl e. ', . : ·· Demodulator One Shot If the one shot is proper ly adju sted, the data is recoverabl e with tape speed var iation in excess of ±30 percent from nomin al speed.
Figure 2 shows the word and timing formats for the BIT BOFFER system. A typical system might use ASCII characters se nt in the Universa l Asynchronous Data format that consists of a start bit, the ASCII code starting with the least significant bit, a parity bit, an d two stop bits. The width of eac h bit is set by the data rate. If we're working with 8 bit bin ary data instead of ASCII characters, we send a start bit, eight bits of data beginning with the least significant bit, an optional parity bit, and then two sto p bits.
The receiver uses a quad automotive comparator to perform zero crossing detection (1 and 2), reset the timing capacitor (3), and sense the capaci to r voltage (4). This is routed to a dual D flop that detects ones and zeros with one side and combines the clocks with the other. A dual four bit shift register is on e possible route to a simpler transmitter. The actual circuits are still under test. - Photo 2: This is how the BIT BOFFER mates with a Southwest Technical Products Corporation UART adapter board in a "piggy back" fashion.